GenISSLib: Instruction Set Simulator Library Generator

Instruction set simulators are useful for processor simulation, either architecture or micro-architecture simulation. Architecture simulation, also called functional simulation, refers to simulation of the processor instruction set, whereas micro-architecture simulation refers to simulation of the components inside the processor such as pipelines, caches, functional units, branch predictors.

Implementing the instruction set into a software instruction set simulator is needed for developping and testing software before the target processor is available or for analyzing softwares without disturbing their execution.

To go from the instruction set specification to a software implementation of the instruction set, it is convenient to have a description language for easily describing the instruction encoding, but most description languages are restricted to only few syntaxical constructions for describing the instructions behavior. Beside, it is important to have a multipurpose instruction decoder as needs evolves.

GenISSLib (for Instruction Set Simulator Library Generator) is intended for developping instruction decoder of such instruction set simulators. It uses a description language for describing instruction encoding. C source code blended with the description language allow the use of complex instruction behaviors, or even more functionalities like disassembling, binary translation and system calls translation.

• Installing GenISSLib: a Quick guide to install GenISSLib
• Source documentations
  • Alpha System Library source documentation: Alpha System Libray doxygen documentation
  • GenISSLib source documentation: GenISSLib doxygen documentation
  • Memory Library source documentation: Memory library doxygen documentation