MicroLib: A Modular Simulation Library

Processor architecture simulation is the key method used by micro-architecture researchers for evaluating the performance and usefulness of new architecture ideas. Micro-Architecture simulation often consists of writing very large software programs describing the detailed behaviour of processors, i.e., what is happening in the processor at every clock cycle, the architecture performance being often measured in numbers of cycles. While these simulators are not as detailed as circuit-level models, the software complexity is very much tied to the architecture complexity itself, and with high-performance processors quickly evolving from a few million transistors in the 1990s to a billion transistors or more in 2005, simulators are becoming excessively complex pieces of software, which are very time-consuming to develop and modify.

Consequently, a single research group can no longer afford to develop a whole new processor simulator with state-of-the-art components as part of its normal research activities, i.e., in order to evaluate a few architecture ideas. As a result, most researchers rely on available models, and especially monolithic simulators, i.e., built as a single piece of software describing a full processor architecture; but a processor architecture is typically composed of several tens of components (cache, scheduler, branch predictions…), which have evolved differently over the years, and more importantly, researchers are usually specialized in just one or a few of these components. Because monolithic simulators do not reflect the modularity of processor architectures, it can be exceedingly difficult to update one or a few architecture components, or to extract a component proposed and implemented by a researcher in order to compare it with other similar components.

This situation has severe consequences on micro-architecture research: (1) researchers develop their ideas on outdated architecture models because they lack alternatives, (2) simulator development time is quickly increasing and researchers have no simple means for reusing and exploiting the development effort of other researchers, (3) researchers have no reasonably rigorous way to compare their performance results, and consequently, these results are often unverifiable and unreliable, (4) the discrepancy between the software structure and the processor structure is a source of inaccuracy sometimes leading researchers to propose unrealistic architectures, (5) and as result, it hinders the take-up of architecture ideas from academia by industry.

In the past few years, the INRIA Alchemy group, together with CEA, University of Paris Sud, University of Toulouse and University of Paris 6, has been focusing on an alternative approach to processor simulation called modular simulation within a project called MicroLib. The principle of modular simulation is to reflect the processor structure in the software simulator structure, alleviating many of the above mentioned issues. The goal of MicroLib is to advocate for a change of methodology in processor architecture research, by encouraging architecture researchers to use modular simulation environments, and by setting up a central library where researchers could easily share, reuse and compare architecture ideas through simulator components.

For that purpose, we have been developing the MicroLib library since 2002. MicroLib is a repository of micro-architecture simulator components developed using modular simulation environments. Even though most of the current MicroLib modules are developed using SystemC, a de facto modular simulation environment in the embedded domain supported by more than 50 companies, MicroLib aims at supporting and encouraging modular simulation rather than a single environment like SystemC. Currently, we are cooperating with the Liberty group at Princeton to develop wrappers which can make SystemC and Liberty interoperable in order to share modules. Rather than a competitor to existing modular simulation environments like Liberty, or even monolithic simulators like SimpleScalar, we want MicroLib to be viewed as an open and, possibly federating, project that will try to build the largest possible library through extensive wrapper development and environment standardization.

Currently, MicroLib contains modules corresponding to the main processor components (caches, branch prediction,…), a few full processor models (a generic superscalar processor simulator called OoOSysC, a PowerPC750 embedded processor simulator), and tools for speeding up simulation. In a recent article published at MICRO in 2004, the INRIA Alchemy group has shown that the lack of a methodology for easily comparing simulation results may have a significant impact on research choices.

The MicroLib project may become part of the Common Simulation Platform action of the HiPEAC European network. The Liberty project, which has been a leading proponent of the modular simulation approach, and the MicroLib project are currently investigating a joint modular simulation environment and repository, with the prospect of setting a common modular simulation standard in the US and Europe in order to speed up adoption.